ac6502 processor core
License : The MIT license
Description language : Verilog
Features :
- 6502 instruction set
- synthesizable
- two-stage pipeline
Version 0.6
first released version
source
FPGA implement
on
Terasic DE1
(aka
Cyclone II Starter Kit)
- Core Clock 12.6MHz = 27*(7/15)
- Total Area 3822LE's (except memory cell)
- firmware : Woz monitor
- PS/2 keyboard
- VGA monitor (640x400 70Hz)
Version 080928
source
for Altera Quartus II 8.0sp1 Web Edition