ac68 processor core
License : The MIT license
Description language : Verilog
Features :
- 6800 instruction set
- synthesizable
- two-stage pipeline
Version 0.6
first released version
source
FPGA implement
on
Terasic DE1
(aka
Cyclone II Starter Kit)
- Core Clock 11.09MHz = 27*(23/56)
- Total Area 2553LE's (except memory cell)
- firmware : MIKBUG
- Serial parameter : 9600bps,8bit,no parity,1 stopbit
with local echo-back and caps lock for convenience
-
Micro BASIC runnable
Version 080818
source
for Altera Quartus II 8.0sp1 Web Edition